DBGMD=HALT, IDLEBEN=DISABLED, STEN=DISABLED, OVFDEN=DISABLED, NOUPD=INACTIVE, OVFSEN=DISABLED, OVFIEN=DISABLED, STSEL=EPCANT0, HALTEN=DISABLED, STESEL=FALLING, DIVST=OUTPUT_HIGH, HALTIEN=DISABLED
Module Control
| OVFIEN | EPCA Counter Overflow/Limit Interrupt Enable. 0 (DISABLED): Disable the EPCA counter overflow/limit event interrupt. 1 (ENABLED): Enable the EPCA counter overflow/limit event interrupt. |
| OVFDEN | EPCA Counter Overflow/Limit DMA Request Enable. 0 (DISABLED): Do not request DMA data when a EPCA counter overflow/limit event occurs. 1 (ENABLED): Request DMA data when a EPCA counter overflow/limit event occurs. |
| OVFSEN | EPCA Counter Overflow/Limit Synchronization Signal Enable. 0 (DISABLED): Do not send a synchronization signal when a EPCA counter overflow/limit event occurs. 1 (ENABLED): Send a synchronization signal when a EPCA counter overflow/limit event occurs. |
| HALTIEN | EPCA Halt Input Interrupt Enable. 0 (DISABLED): Do not generate an interrupt if the EPCA halt input is high. 1 (ENABLED): Generate an interrupt if the EPCA halt input is high. |
| NOUPD | Internal Register Update Inhibit. 0 (INACTIVE): The EPCA registers will automatically load any new update values after an overflow/limit event occurs. 1 (ACTIVE): The EPCA registers will not load any new update values after an overflow/limit event occurs. |
| IDLEBEN | Idle Bypass Enable. 0 (DISABLED): The EPCA module will stop running when the core halts (idle). 1 (ENABLED): The EPCA module will continue normal operation when the core halts (idle). |
| DBGMD | EPCA Debug Mode. 0 (HALT): A debug breakpoint will stop the EPCA counter/timer. 1 (RUN): The EPCA will continue to operate while the core is halted in debug mode. |
| HALTEN | Halt Input Enable. 0 (DISABLED): The Halt input (PB_HDKill) does not affect the EPCA counter/timer. 1 (ENABLED): An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer. |
| STSEL | Synchronous Input Trigger Select. 0 (EPCANT0): Select input trigger 0, 1 (EPCANT1): Select input trigger 1, 2 (EPCANT2): Select input trigger 2, 3 (EPCANT3): Select input trigger 3, |
| STESEL | Synchronous Input Trigger Edge Select. 0 (FALLING): A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer. 1 (RISING): A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer. |
| STEN | Synchronous Input Trigger Enable. 0 (DISABLED): Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger. 1 (ENABLED): Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met. |
| DIVST | Clock Divider Output State. 0 (OUTPUT_HIGH): The clock divider is currently in the first half-cycle. 1 (OUTPUT_LOW): The clock divider is currently in the second half-cycle. |
| DIV | Current Clock Divider Count. |